Bias Temperature Instability and Reliability in CMOS Transistors
This community investigates how electrical stress causes transistors to degrade over time, specifically focusing on the mechanisms behind threshold voltage shifts and reliability failures in integrated circuits.
The research centers on Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI), analyzing how these phenomena affect gate oxides, interface traps, and carrier degradation in CMOS, FinFET, and VDMOS transistors. Key methods include modeling aging and stress recovery, characterizing random telegraph noise, and assessing impacts on SRAM cells and digital circuits. The work also addresses hardware security, including the detection of hardware Trojans and soft errors, often using machine learning techniques to identify anomalies in device behavior.
Silicon research accounts for 0.4% of this community's output, with 1,586 papers, while Germanium contributes 0.3% and Hafnium 0.4%. The community publishes primarily in the Journal of Applied Physics, IEEE Transactions on Electron Devices, and Microelectronics Reliability, comprising 5,975 total papers. Recent work continues to focus on physics-consistent reliability frameworks, power-law kinetics in SiC MOSFETs, and the impact of radiation-induced interface traps in silicon-based devices.