Atomic Layer Deposition and Gate Engineering for Advanced Transistors
This community focuses on the fabrication of ultra-thin oxide layers and the design of transistor gate structures to enable next-generation semiconductor devices.
The research centers on atomic layer deposition (ALD) and chemical vapor deposition techniques for creating high-k dielectric materials, particularly hafnium oxide, which serves as the insulating layer in modern transistors. Key technical challenges addressed include controlling work function, managing interface traps, and optimizing threshold voltage in field-effect transistors (FETs). The work extends to specific device architectures such as tunnel field-effect transistors (TFETs), gate-all-around nanowires, and junctionless transistors, aiming to improve electrical characteristics and reliability in silicon, germanium, and compound semiconductor platforms.
The largest share of the community's output is found in hafnium research, accounting for 22.1% of all hafnium research, and 6,239 papers here. Silicon contributes the highest paper count within this group, with 8,585 papers, representing 2.2% of silicon research.
The community comprises 42,322 papers, published primarily in Applied Physics Letters, Journal of Applied Physics, and Japanese Journal of Applied Physics.
Recent work includes novel atomic layer processes for semiconductor manufacturing, such as area selective deposition and atomic layer annealing, as well as studies on self-passivation in metal-semiconductor contacts and the electrical performance of gate-all-around nanowire TFETs.